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HDSP-210x Series
Eight Character 5 mm and 7 mm Smart Alphanumeric Displays
Data Sheet
HDSP-210x Series, HDSP-211x Series, HDSP-250x Series
Description The HDSP-210x/-211x/-250x series of products is ideal for applications where displaying eight or more characters of dot matrix information in an aesthetically pleasing manner is required. These devices are 8-digit, 5 x 7 dot matrix, alphanumeric displays and are all packaged in a standard 15.24 mm (0.6 inch) 28 pin DIP. The on-board CMOS IC has the ability to decode 128 ASCII characters which are permanently stored in ROM. In addition, 16 programmable symbols may be stored in on- board ROM, allowing considerable flexibility for displaying additional symbols and icons. Seven brightness levels provide versatility in adjusting the display intensity and power consumption. The HDSP-210x/-211x/-250x products are designed for standard microprocessor interface techniques. The display and special features are accessed through a bidirectional 8-bit data bus.
Features * X stackable (HDSP-21xx) * XY stackable (HDSP-250x) * 128 sharacter ASCII decoder * Programmable functions * 16 user definable characters * Multi-level dimming and blanking * TTL compatible CMOS IC * Wave solderable Applications * Computer peripherals * Industrial instrumentation * Medical equipment * Portable data entry devices * Cellular phones * Telecommunications equipment * Test equipment
Device Selection Guide Font Height
0.2 inches 0.27 inches
AlGaAs Red
HDSP-2107 HDSP-2504
High Efficiency Red
HDSP-2112 HDSP-2502
Orange
HDSP-2110 HDSP-2500
Yellow
HDSP-2111 HDSP-2501
Green
HDSP-2113 HDSP-2503
Package Dimensions
PIN FUNCTION ASSIGNMENT TABLE 42.59 (1.677) 5.33 TYP. (0.210) PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FUNCTION PIN # RST 15 FL 16 A0 17 A1 18 A2 19 A3 20 DO NOT CONNECT 21 DO NOT CONNECT 22 DO NOT CONNECT 23 A4 24 CLS 25 CLK 26 WR 27 VDD 28 FUNCTION GND (SUPPLY) GND (LOGIC) CE RD D0 D1 NO PIN NO PIN D2 D3 D4 D5 D6 D7
28
4.81 (0.189) 0 1 PIN DESIGNATION 2.69 (0.106) 2.64 SYM. (0.104) 1 2 3 4 5 6 7 9.8 (0.386)
19.58 (0.771)
PIN 1 IDENTIFIER
PART NUMBER DATE CODE [4] HDSP-21XX YYWW YZ COO
LUMINOUS INTENSITY CATEGORY COLOR BIN (NOTE 3) COUNTRY OF ORIGIN
IMAGE PLANE (FOR REFERENCE ONLY) 2.01 (0.08)
0.25 (0.010)
5.31 (0.209)
4.79 SYM. (0.189)
DIA. 0.51 0.13 TYP. (0.020 0.005)
3.92 TYP. (0.154) 2.54 0.13 TYP. (NON-ACCUM) (0.100 0.005)
2.17 SYM. (0.085) 15.24 (0.600)
NOTES: 1. DIMENSIONS ARE IN mm (INCHES). 2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON ALL DIMENSIONS IS 0.25 mm (0.010 INCH). 3. FOR YELLOW AND GREEN DEVICES ONLY.
Absolute Maximum Ratings
Supply Voltage, VDD to Ground[1] Operating Voltage, VDD to Ground[2] Input Voltage, Any Pin to Ground Free Air Operating Temperature Range, TA[3] Storage Temperature Range, TS Relative Humidity (non-condensing) Soldering Temperature [1.59 mm (0.063 in.) Below Body] Solder Dipping Wave Soldering ESD Protection @ 1.5 k, 100 pF -0.3 to 7.0 V 5.5 V -0.3 to VDD +0.3 V -45C to +85C -55C to +100C 85%
260C for 5 secs 250C for 3 secs VZ = 4 kV (each pin)
Notes: 1. Maximum Voltage is with no LEDs illuminated. 2. 20 dots ON in all locations at full brightness. 3. Maximum supply voltage is 5.25 V for operation above 70C.
ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO AVOID STATIC DISCHARGE. 2
Package Dimensions
70.87 (2.790) 8.84 TYP. (0.348) 4.51 (0.178) 28 6.96 TYP. (0.274) 9.70 (0.382) 0 1 1 PIN DESIGNATION PIN 1 IDENTIFIER 2 3 4 5 6 7 19.41 (0.764) 5.08 TYP. (0.200)
PIN FUNCTION ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FUNCTION RST FL A0 A1 A2 A3 DO NOT CONNECT DO NOT CONNECT DO NOT CONNECT A4 CLS CLK WR VDD PIN # 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FUNCTION GND (SUPPLY) GND (LOGIC) CE RD D0 D1 NO PIN NO PIN D2 D3 D4 D5 D6 D7
PART NUMBER DATE CODE [4] HDSP-250X YYWW YZ COO
LUMINOUS INTENSITY CATEGORY COLOR BIN (NOTE 3) COUNTRY OF ORIGIN
0.38 (0.015)
IMAGE PLANE (FOR REFERENCE ONLY) 2.01 (0.79)
6.60 (0.260)
19.01 SYM. (0.749)
2.54 0.13 TYP. (NON-ACCUM) (0.100 0.005)
DIA. 0.51 0.13 TYP. (0.200 0.005)
3.91 TYP. (0.154) 15.24 (0.600)
2.08 SYM. (0.082)
NOTES: 1. DIMENSIONS ARE IN mm (INCHES). 2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON ALL DIMENSIONS IS 0.25 mm (0.010 INCH). 3. FOR YELLOW AND GREEN DEVICES ONLY.
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ASCII Character Set HDSP-210X, HDSP-211X, HDSP-250X Series
D7 D6
BIT S
D5 D4 D3 D2 D1 D0 ROW 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F COLUMN
0 0
0 0
0 0 0
0 1
0 0 1
1 2
0 0 0
1 3
0 1 1
0 4
0 1 0
0 5
0 1 1
1 6
0 1 0
1 7
1 X 1
X 8-F 16 U S E R D E F I N E D C H A R A C T E R S
X
Recommended Operating Conditions Parameter Symbol
Supply Voltage VDD
Minimum
4.5
Nominal
5.0
Maximum
5.5
Units
V
4
Electrical Characteristics Over Operating Temperature Range (-45C to +85C) 4.5 V < VDD < 5.5 V, unless otherwise specified TA = 25C -45C < TA < + 85C VDD = 5.0 4.5 V < VDD < 5.5 V Parameter Symbol Typ. Max. Min. Max.
Input Leakage (Input without pullup) Input Current (Input with pullup) IDD Blank IDD 8 digits 12 dots/character[1,2] IDD 8 digits 20 dots/character[1,2,3,4] Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low D0-D7 Output Voltage Low CLK High Level Output Current Low Level Output Current Thermal Resistance IC Junction-to-Case IIH IIL IIPL -11 -18 1.0 -1.0 -30
Units
A
Test Conditions
VIN = 0 to VDD, pins CLK, D0-D A0-A4 VIN = 0 to VDD, pins CLS, RST, WR, RD, CE, FL VIN = VDD "V" on in all 8 locations "#" on in al locations
A
IDD (BLK) IDD(V) IDD(#) VIH VIL VOH VOL VOL IOH IOL RqJ-C
0.5 200 300
3.0 255 370 2.0 GND -0.3 V 2.4
4.0 330 430 VDD +0.3 0.8
mA mA mA V V V
VDD = 4.5 V, IOH = -40 A VDD = 4.5 V, IOL = 1.6 mA VDD = 4.5 V, IOL = 40 A VDD = 5.0 V VDD = 5.0 V
0.4 0.4 -60 50 15
V V mA mA C/W
Notes: 1. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x IDD (#). 2. Maximum IDD occurs at -55C. 3. Maximum IDD(#) = 355 mA at VDD = 5.25 V and IC TJ = 150C. 4. Maximum IDD(#) = 375 mA at VDD = 5.5 V and IC TJ = 150C.
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Optical Characteristics at 25C[1] VDD = 5.0 V at Full Brightness Part Number
HDSP-2107 -2504 HDSP-2112 -2502 HDSP-2110 -2500 HDSP-2111 -2501 HDSP-2113 -2503
Description
AlGaAs HER Orange Yellow High Performance Green
Luminous Intensity Character Average (#) Iv (mcd) Min.
8.0 2.5 2.5 2.5 2.5
Typ.
15.0 7.5 7.5 7.5 7.5
Peak Wavelength lPeak (nm)
645 635 600 583 568
Dominant Wavelength ld (nm)
637 626 602 585 574
Note: 1. Refers to the initial case temperature of the device immediately prior to measurement.
AC Timing Characteristics Over Temperature Range (-45C to +85C) 4.5 V < VDD < 5.5 V, unless otherwise specified Reference Number Symbol Description
1 tACC Display Access Time Write Read Address Setup Time to Chip Enable Chip Enable Active Time[2,3] Write Read Address Hold Time to Chip Enable Chip Enable Recovery Time Chip Enable Active Prior to Rising Edge of[2,3] Write Read Chip Enable Hold Time to Rising Edge of Read/Write Signal[2,3] Write Active Time Data Write Setup Time Data Write Hold Time Chip Enable Active Prior to Valid Data Read Active Prior to Valid Data Read Data Float Delay Reset Active Time[4]
Min.[1]
210 230 10 140 160 20 60 140 160 0 100 50 20 160 75 10 300
Units
ns ns
2 3
tACS tCE
ns ns ns
4 5 6
tACH tCER tCES
ns ns ns ns ns ns ns ns ns
7 8 9 10 11 12 13
tCEH tW tWSU tWH tR tRD tDF tRC
Notes: 1. Worst case values occur at an IC junction temperature of 150C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. 4. The display must not be accessed until after 3 clock pulses (110 s min. using the internal refresh clock) after the rising edge of the reset line.
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AC Timing Characteristics Over Temperature Range (-45C to +85C) 4.5 V < VDD < 5.5 V, unless otherwise specified Symbol Description 25C Typ. Min.[1]
FOSC FRF[2] FFL[3] tST[4] Oscillator Frequency Display Refresh Rate Character Flash Rate Self Test Cycle Time 57 256 2 4.6 28 128 1 9.2
Units
kHz Hz Hz sec
Notes: 1. Worst case values occur at an IC junction temperature of 150C. 2. FRF = FOSC/224. 3. FFL = FOSC/28,672. 4. tST = 262,144/FOSC.
Write Cycle Timing Diagram
1
A0 -A4 FL 4 2 3 5 2
CE 6 8 7
WR 10 9
D0 -D7
INPUT PULSE LEVELS: 0.6 V to 2.4 V
7
Read Cycle Timing Diagram
1
A0 -A4 FL 2 3 4 5 2
CE 6 11 7
RD 12 13
D0 -D7
INPUT PULSE LEVELS: 0.6 V to 2.4 V OUTPUT REFERENCE LEVELS: 0.6 V to 2.2 V OUTPUT LOADING = 1 TTL LOAD AND 100 pF
Relative Luminous Intensity vs. Temperature
3.5
RELATIVE LUMINOUS INTENSITY (NORMALIZED TO 1 AT 25C)
3.0 2.5 2.0 1.5
HER HDSP-2112/2502 ORANGE HDSP-2110/2500 YELLOW HDSP-2111/2501
GREEN 1.0 HDSP-2113/2503 0.5 0 -55 -45 -35 -15 5 25 45 65 85
TA - AMBIENT TEMPERATURE - C
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Electrical Description
Pin Function RESET (RST, pin 1) FLASH (FL, pin 2) ADDRESS INPUTS (A0-A4, pins 3-6, 10) Description Initializes the display. FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A3-A4. Each location in memory has a distinct address. Address inputs (A 0 -A 2 ) select a specific location in the Character RAM, the Flash RAM or a particular row in the UDC (User-Defined Character) RAM. A 3-A 4 are used to select which section of memory is accessed. Table 1 shows the logic levels needed to access each section of memory. Table 1. Logic Levels to Access Memory Section of Memory FL A4 A3
Flash RAM UDC Address Register UDC RAM Control Word Register Character RAM 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1
A2 A1 A0
Char. Address Don't Care Row Address Don't Care Character Address
CLOCK SELECT (CLS, pin 11) CLOCK INPUT/OUTPUT (CLK, pin 12) WRITE (WR, pin 13) CHIP ENABLE (CE, pin 17) READ (RD, pin 18) DATA Bus (D0-D7, pins 19, 20, 23-28) GND (SUPPLY) (pin 15) GND (LOGIC) (pin 16) VDD (POWER) (pin 14)
Used to select either an internal (CLS = 1) or external (CLS = 0) clock source. Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. Data is written into the display when the WR input is low and the CE input is low. Must be at a logic low to read or write data to the display and must go high between each read and write cycle. Data is read from the display when the RD input is low and the CE input is low. Used to read from or write to the display. Analog ground for the LED drivers. Digital ground for internal logic. Positive power supply input.
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UDC ADDR REGISTER EN
A3 A4 FL CE RD WR D0-D7 UDC ADDR CLR PRE SET
10
A3 A4 FL CE UDC RAM A3 A4 FL CE EN RD WR DOT D0-D4 A0-A2 DATA UDC ADDR ROW SET EN D0-D4 EN ASCII DECODER D0-D6 ROW SEL SELF TEST DOT DATA DOT DATA DOT DRIVERS TIMING 8 5x7 LED CHARACTERS FL CE 8x8 EN CHARACTER RD D0-D6 RAM WR D7 D0-D7 A0-A2 RESET CHAR ADDR RESET EN FLASH RD DATA WR FLASH D0 RAM A0-A2 RESET CHAR ADDR ROW DRIVERS TIMING CONTROL WORD REGISTER EN 0 INTENSITY RD 1 WR 2 FLASH D0-D7 3 BLINK 4 RESET SELF TEST 6 SELF TEST 7 RESULT SELF TEST SELF TEST IN VISUAL TEST ROM TEST SELF TEST CLR START TEST OK FLASH TEST OK CLR2 CHAR ADDR TIMING AND CONTROL ROW SET TIMING CLR1 INTENSITY FLASH BLINK RESET CLOCK
RD WR D0-D7 A0-A2 A3 A4 FL CE
A3 A4 FL CE
RST
CLK
CLS
OCS
Figure 1. HDSP-210X/-211X/-212X/-250X internal block diagram.
Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP210X/-211X/-250X displays. The CMOS IC consists of an 8 byte Character RAM, an 8 bit Flash RAM, a 128 character ASCII decoder, a 16 character UDC RAM, a UDC Address
Register, a Control Word Register, and refresh circuitry necessary to synchronize the decoding and driving of eight 5 x 7 dot matrix characters. The major user-accessible portions of the display are listed below:
Character RAM Flash RAM User-Defined Character RAM (UDC RAM) User-Defined Character Address Register (UDC Address Register) Control Word Register
This RAM stores either ASCII character data or a UDC RAM address. This is a 1 x 8 RAM which stores Flash data. This RAM stores the dot pattern for custom characters. This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. This register allows the user to adjust the display brightness, flash individual characters, blink, self test, or clear the display.
Character RAM Figure 2 shows the logic levels needed to access the HDSP-210X/-211X/-250X Character RAM. During a normal access, the CE = "0" and either RD = "0" or WR = "0." However, erroneous data may be written into the Character RAM if the address lines are unstable when CE = "0" regardless of the logic levels of the RD or WR lines. Address lines A0-A2 are used to select the location in the Character RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D7 is used to differentiate between the ASCII character and a UDC RAM address. D7 = 0 enables the ASCII decoder and D7 = 1 enables the UDC RAM. D0D6 are used to input ASCII data and D0-D3 are used to input a UDC address.
RST 1
CE 0
WR 0 0 1 1
RD 0 1 0 1
UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED
CONTROL SIGNALS
FL 1
A4 1
A3 1
A2
A1
A0 000 = LEFT MOST 111 = RIGHT MOST
CHARACTER ADDRESS
CHARACTER RAM ADDRESS
D7 0 1
D6
D5
D4
D3
D2
D1
D0
128 ASCII CODE X X X UDC CODE
CHARACTER RAM DATA FORMAT
DIG0 000
DIG1 001
DIG2 010
DIG3 011
DIG4 100
DIG5 101
DIG6 110
DIG7 111
SYMBOL IS ACCESSED IN LOCATION SPECIFIED BY THE CHARACTER ADDRESS ABOVE DISPLAY 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
Figure 2. Logic levels to access the character RAM.
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UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address Register. The UDC Address Register is eight bits wide. The lower four bits (D0-D3) are used to select one of the 16 UDC locations. The upper four bits (D4-D7) are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed. To completely specify a 5 x 7 character, eight write cycles are required. One cycle is used to store the UDC RAM address in the UDC Address Register and seven cycles are used to store dot data in the UDC RAM. Data is entered by rows and one cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an "F." A0-A2 are used to select the row to be accessed and D0-D4 are used to transmit the row dot data. The upper three bits (D5-D7) are ignored. D0 (least significant bit) corresponds to the right most column of the 5 x 7 matrix and D4 (most significant bit) corresponds to the left most column of the 5 x 7 matrix. Flash RAM Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input is used to select the Flash RAM while address lines A3-A4 are ignored. Address lines A0-A2 are used to select the location in the Flash RAM to store the attribute. D0 is used to store or remove the flash attribute. D0 = "1" stores the attribute and D0 = "0" removes the attribute. When the attribute is enabled through bit 3 of the Control Word and a "1" is stored in the Flash RAM, the corresponding character will flash at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock the flash rate can be calculated by dividing the clock frequency by 28,672.
RST 1
CE 0
WR 0 0 1 1
RD 0 1 0 1
UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED
CONTROL SIGNALS
FL 1
A4 0
A3 0
A2 X
A1 X
A0 X
UDC ADDRESS REGISTER ADDRESS
D7 X
D6 X
D5 X
D4 X
D3
D2
D1
D0
UDC CODE
UDC ADDRESS REGISTER DATA FORMAT
RST 1
CE 0
WR 0 0 1 1
RD 0 1 0 1
UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED
CONTROL SIGNALS
FL 1
A4 0
A3 1
A2
A1
A0 000 = ROW 1 110 = ROW 7
ROW SELECT
UDC RAM ADDRESS
D7 X
D6 X
D5 X
D4
D3
D2 DOT DATA
D1
D0
C O L 1 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
UDC RAM DATA FORMAT
C O L 5
Figure 3. Logic levels to access a UDC character.
CCC OOO LLL 123 D 4 D 3 D2 111 100 100 111 100 100 100 IGNORED
C O L 4 D1 1 0 0 1 0 0 0
C O L 5 D0 1 0 0 0 0 0 0
ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7
UDC CHARACTER ***** * * **** * * *
HEX CODE 1F 10 10 1D 10 10 10
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED
Figure 4. Data to load ""F'' into the UDC RAM.
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Control Word Register Figure 6 shows how to access the Control Word Register. This 8-bit register performs five functions: Brightness control, Flash RAM control, Blinking, Self Test, and Clear. Each function is independent of the others; however, all bits are updated during each Control Word write cycle. Brightness (Bits 0-2) Bits 0-2 of the Control Word adjust the brightness of the display. Bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0-2 also vary the average value of IDD. IDD can be calculated at any brightness level by multiplying the percent brightness level by the value of IDD at the 100% brightness level. These values of IDD are shown in Table 2. Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a"1," the output of the Flash RAM is checked. If the content of a location in the Flash RAM is a "1," the associated digit will flash at approximately 2 Hz. For an external clock, the blink rate can be calculated by driving the clock frequency by 28,672. If the flash enable bit of the Control Word is a "0," the content of the Flash RAM is ignored. To use this function with multiple display systems, see the Display Reset section. Blink Function (Bit 4) Bit 4 of the Control Word is used to synchronize blinking of all eight digits of the display. When this bit is a "1" all eight digits of the display will blink at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems, see the Display Reset section.
RST 1
CE 0
WR 0 0 1 1
RD 0 1 0 1
UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED
CONTROL SIGNALS FL 0 A4 X A3 X A2 A1 A0 000 = LEFT MOST 111 = RIGHT MOST
CHARACTER ADDRESS
FLASH RAM ADDRESS D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 0 1 REMOVE FLASH AT SPECIFIED DIGIT LOCATION STORE FLASH AT SPECIFIED DIGIT LOCATION
FLASH RAM DATA FORMAT 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
Figure 5. Logic levels to access the flash RAM.
RST 1 CE 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED
CONTROL SIGNALS
FL 1
A4 1
A3 0
A2 X
A1 X
A0 X
CONTROL WORD ADDRESS
D7 C
D6 S
D5 S
D4 BL
D3 F
D2 B
D1 B
D0 B 0 1 0 1 0 1 0 1 100% 80% 53% BRIGHTNESS 40% CONTROL 27% LEVELS 20% 13% 0%
0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 DISABLE FLASH 1 ENABLE FLASH 0 DISABLE BLINKING 1 ENABLE BLINKING 0 1
X NORMAL OPERATION; X IS IGNORED X START SELF TEST; RESULT GIVEN IN X X = 0 FAILED X = 1 PASSED
0 NORMAL OPERATION 1 CLEAR FLASH AND CHARACTER RAMS CONTROL WORD DATA FORMAT 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
Figure 6. Logic levels to access the control word register
Table 2. Current Requirements at Different Brightness Levels VDD = 5.0 V % Current at 25C Symbol D2 D1 D0 Brightness Typ.
IDD (V) 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 100 80 53 40 27 20 13 200 160 106 80 54 40 26
Units
mA mA mA mA mA mA mA
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Self Test Function (Bits 5, 6) Bit 6 of the Control Word Register is used to initiate the self test function. Results of the internal self test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = "1" indicates a passed self test and bit 5 = "0" indicates a failed self test. Setting bit 6 to a logic 1 will start the self test function. The built-in self test function of the IC consists of two internal routines which exercise major portions of the IC and illuminate all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to "1." The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 KHz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self test function, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except for bit 5, the Flash RAM is cleared, and the UDC Address Register is set to all ones. Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a "1" will start the clear function. Three clock cycles (110 ms minimum using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been completed, bit 7 will be reset to a "0." The ASCII character code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with "0"s. The UDC RAM, UDC Address Register, and the remainder of the Control Word are unaffected.
RST 0 CE 1 WR X RD X FL X A4 -A0 D7 -D0 X X
Display Reset Figure 7 shows the logic levels needed to Reset the display. The display should be Reset on Power-up. The external Reset clears the Character RAM, Flash RAM, Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 s minimum using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Character code for a space (20H) will be loaded into the Character RAM to blank the display. The Flash RAM and Control Word Register are loaded with all "0"s. The UDC RAM and UDC Address Register are unaffected. All displays which operate with the same clock source must be simultaneously reset to synchronize the Flashing and Blinking functions. Mechanical and Electrical Considerations The HDSP-210X/-211X/-250X are 28 pin dual-in-line packages with 26 external pins. The devices can be stacked horizontally and vertically to create arrays of any size. The HDSP-210X/-211X/-250X are designed to operate continuously from -45C to +85C with a maximum of 20 dots on per character at 5.25 V. Illuminating all thirty-five dots at full brightness is not recommended. The HDSP-210X/-211X/-250X are assembled by die attaching and wire bonding 280 LED chips and a CMOS IC to a thermally conductive printed circuit board. A polycarbonate lens is placed over the PC board creating an air gap over the LED wire bonds. A protective cap creates an air gap over the CMOS IC. Backfill epoxy environmentally seals the display package. This package construction makes the display highly tolerant to temperature cycling and allows wave soldering. The inputs to the IC are protected against static discharge and input current latchup. However, for best results standard CMOS handling precautions should be used. Prior to use, the HDSP-210X/-211X/-250X should be stored in antistatic tubes or in conductive material. During assembly, a grounded conductive work area should be used, and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static buildup. Input current latchup is caused when the CMOS inputs are subjected to either a voltage below ground (VIN < ground) or to a voltage higher than VDD (VIN > VDD) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected either to ground or to VDD. Voltages should not be applied to the inputs until VDD has been applied to the display.
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE NOTE: IF RST, CE, AND WR ARE LOW, UNKNOWN DATA MAY BE WRITTEN INTO THE DISPLAY.
Figure 7. Logic levels to reset the display.
14
Thermal Considerations The HDSP-210X/-211X/-212X/250X have been designed to provide a low thermal resistance path for the CMOS IC to the 26 package pins. Heat is typically conducted through the traces of the printed circuit board to free air. For most applications no additional heatsinking is required. Measurements were made on a 32 character display string to determine the thermal resistance of the display assembly. Several display boards were constructed using 0.062 in. thick printed circuit material, and one ounce copper 0.020 in. traces. Some of the device pins were connected to a heatsink formed by etching a copper area on the printed circuit board surrounding the display. A maximally metallized printed circuit board was also evaluated. The junction temperature was measured for displays soldered directly to these PC boards, displays installed in sockets, and finally displays installed in sockets with a filter over the display to restrict airflow. The results of these thermal resistance measurements, RqJ-A are shown in Table 3 and include the effects of RqJ-C. Ground Connections Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the analog ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long interconnections between the display and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. The logic ground should be connected to the same ground potential as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground which can withstand the current introduced by the switching LED drivers. When separate ground connections are used, the analog ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltage below -0.3 V can cause all dots to be on. Voltage above +0.3 V can cause dimming and dot mismatch. Table 3. Thermal Resistance, qJA, Using Various Amounts of Heatsinking Material Heatsinking Metal W/Sockets W/O Sockets per Device W/O Filter W/O Filter sq. in. (Avg.) (Avg.)
0 1 3 Max. Metal 4 Board Avg 31 31 30 29 30 30 28 26 25 27
Soldering and Post Solder Cleaning Instructions for the HDSP-210X/-211X/-250X The HDSP-210X/-211X/-250X may be hand soldered or wave soldered with SN63 solder. When hand soldering, it is recommended that an electronically temperature controlled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315C (600F). For wave soldering, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245C 5C (473F 9F), and the dwell in the wave should be set between 11 /2 to 3 seconds for optimum soldering. The preheat temperature should not exceed 105C (221F) as measured on the solder side of the PC board. For additional information on soldering and post solder cleaning, see Application Note 1027, Soldering LED Components. Contrast Enhancement The objective of contrast enhancement is to provide good readability in a variety of ambient lighting conditions. For information on contrast enhancement see Application Note 1015, Contrast Enhancement Techniques for LED Displays.
W/Sockets W/Filter (Avg.)
35 33 33 32 33
Units
C/W C/W C/W C/W C/W
Intensity Bin Limits for HDSP-2107 Intensity Range (mcd) Bin Min. Max.
I J K L M 5.12 7.68 11.52 17.27 25.39 9.01 13.52 20.28 30.42 45.63
Color Bin Limits Color
Yellow
Bin
3 4 5 6 7
Color Range (nm) Min. Max.
581.5 584.0 586.5 589.0 591.5 576.0 573.0 570.0 567.0 585.0 587.5 590.0 592.5 595.0 580.0 577.0 574.0 571.5
Note: Test conditions as specified in Optical Characteristic table.
Green
1 2 3 4
Intensity Bin Limits for HDSP-211x and HDSP-250x (Except HDSP-2504) Intensity Range (mcd) Bin Min. Max.
G H I J K 2.50 3.41 5.12 7.68 11.52 4.00 6.01 9.01 13.52 20.28
Note: Test conditions as specified in Optical Characteristic table.
Note: Test conditions as specified in Optical Characteristic table.
Intensity Bin Limit for HDSP-2504 Intensity Range (mcd) Bin
J K L M Note:
Min.
7.68 11.52 17.27 25.91
Max
13.52 20.28 30.42 45.63
Test conditions as specified in Optical Characteristic table.
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3183EN AV02-0629EN - May 9, 2008

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